TSMC has released a roadmap that takes us beyond the 3nm manufacturing node.

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Earlier this week, TSMC’s 2022 Technology Symposium began which included the release of a roadmap by TSMC for its leading-edge process nodes that feature 3nm (N3) and 2nm (N2) chips. The smaller the process node, the larger the number of transistors used inside a chip. And that is important because traditionally, the higher the transistor count, the more powerful and energy-efficient a chip is.

Taiwanese company TSMC owns the world’s largest foundry. This is the business that makes Apple’s chip designs, such as the A15 Bionic, into actual chips (which runs the iPhone 13 series and features 15 billion transistors in each chip). TSMC also makes the M1 chip family, which includes the M1 Ultra, which has 114 billion transistors. Two M1 Max chips are combined to create the M1 Ultra.


  • TSMC will continue to use FinFET field-effect transistors for its 3nm process node while Samsung will debut its gate-all-around transistors with its 3nm chips). On the other hand, TSMC won’t begin using gate-all-around transistors until it starts to ship its 2nm chips. TSMC experts its more cutting-edge chip designing customers to quickly demand N2 when available while the foundry’s less tech-demanding customers will probably decide to stick with a 3nm process node for the next few years to come.

  • The next major process node will be 3nm which Apple hopes to use on next year’s iPhone 15 series. TSMC expects to have five N3 nodes over the next three years. Instead of releasing a new node every two years which was the custom for the foundry and the industry, TSMC will now introduce a new node every two and a half years increasing to every three years with the N2 (2nm) process node. This data is known as the node introduction cadence.

The N3E node reduces power consumption by 34%, or delivers an 18% performance bump. By 2024, the foundry expects to offer its N3P node focusing on performance improvements. And N3S is the density-focused version of the 3nm node. Density tells us how many million transistors can fit into a square mm of space. High density chips allow for more circuits to be placed on a chip while delivering higher operating speed.

The foundry’s first 3nm node to be shipped will start high-volume manufacturing during the second half of this year. Deliveries of 3nm chips will start to take place in early 2023. According to AnandTech, N3 is made for early adopters including Apple who could take advantage of the increase in the performance, power, and area (PPA) delivered by leading-edge nodes.

The 3nm process nodes will be the last from TSMC to deliver the FinFET transistor-based process nodes. These transistors use a design shaped like a “fin” which is where they get their name. TSMC will introduce its 2nm process node technology in 2025.


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